Interconnection structure and methods

ABSTRACT

Interconnection structures for integrated circuits have a first array of cells, at least a second array of cells parallel to the first array, and interconnections disposed for connecting cells of the first array with cells of the second array, at least some of the interconnections being disposed along axes oriented obliquely to the first and second arrays. First and second sets of oblique axes of interconnections may be parallel or opposed to each other. The interconnections may include obliquely slanted pillars or stair-stepped pillars disposed along the oblique axes. Methods for fabricating and using such structures are disclosed.

RELATED APPLICATIONS

[0001] This application is related to copending application Ser. No.10/051,677 filed Jan. 16, 2002 and assigned to the same assignee.

FIELD OF THE INVENTION

[0002] This application relates to interconnection structures especiallyuseful in semiconductor devices such as integrated circuits and memorydevices and relates to methods for fabricating and using suchstructures.

BACKGROUND ART

[0003] Integrated circuits including arrays of memory nodes or logicgates have increased steadily in density. Such integrated circuits haveincluded dynamic random access memory (DRAM) devices, static randomaccess memory (SRAM) devices, programmable read-only memory (PROM)integrated circuits, electrically erasable programmable read-only memory(EEPROM) integrated circuits, write-once read-many (WORM) memorydevices, and logic devices such as programmable logic array (PLA)integrated circuits, among others. Integrated circuits having arrays ofdevices, gates, or memory nodes disposed on multiple levels require“vertical” interconnections or “pillars” to interconnect devices, gates,or memory nodes on one level with other devices, gates, or nodes onother levels. In this context, the term “vertical” differs from itseveryday connotation in that it does not refer to the direction ofgravity. Throughout this specification, the drawings, and the appendedclaims, the term “vertical” refers to a direction generallyperpendicular to a substrate or base plane of an integrated circuit.Also, the term “pillar” referring to an interconnection and the term“vertical interconnection” are used interchangeably to mean aninterconnection communicating between different layers of an integratedcircuit, regardless of the spatial orientation of those differentlayers. Integrated circuits herein include not only monolithicintegrated circuits, but also hybrid integrated circuits and multi-layeror “stacked” modules. The term “cell” herein refers to a functionalelement of an array, such as a memory node, a logic gate, a switchingdevice, a field-effect device, or a semiconductor device.

[0004] There is a continuing need for increased device density inintegrated circuits, including multi-layer integrated circuits and forefficient interconnection structures within such multi-layer integratedcircuits.

BRIEF DESCRIPTION OF DRAWINGS

[0005] To clarify features and advantages of the invention, a detaileddescription of the invention will be rendered by reference to specificembodiments thereof, which are illustrated in the appended drawings. Thesame numbers are used throughout the drawings to refer to like featuresand components. It will be appreciated that these drawings depict onlytypical embodiments of the invention and are therefore not to beconsidered limiting of its scope. The invention will be described andexplained with additional specificity and detail through the use of theaccompanying drawings in which:

[0006]FIG. 1 shows a schematic diagram illustrating elements of a memoryto which interconnection embodiments made in accordance with theinvention may be applied.

[0007]FIG. 2 shows a side elevation cross-sectional view of angledinterconnection embodiments made in accordance with the invention.

[0008]FIG. 3 shows a side elevation cross-sectional view ofstair-stepped interconnection embodiments made in accordance with theinvention.

[0009]FIG. 4A shows a schematic perspective view of a first embodimenthaving a set of interconnections made in accordance with the invention.

[0010]FIG. 4B shows a schematic end elevation view of the embodiment ofFIG. 4A.

[0011]FIG. 4C shows a schematic side elevation view of the embodiment ofFIG. 4A.

[0012]FIG. 5A shows a schematic perspective view of a second embodimenthaving a set of interconnections made in accordance with the invention.

[0013]FIG. 5B shows a schematic side elevation view of a portion of theembodiment of FIG. 5A.

[0014]FIG. 5C shows schematic side elevation views illustrating arelationship between two portions of the embodiment of FIG. 5A.

[0015]FIG. 6 shows a flow chart illustrating a method for fabricating aninterconnection structure in accordance with the invention.

[0016]FIG. 7 shows a side elevation cross-sectional view of a portion ofan embodiment, illustrating a method for performing a fabrication step.

[0017]FIG. 8 shows a cutaway perspective view of a portion of anotherembodiment, illustrating another method for performing a fabricationstep.

DETAILED DESCRIPTION OF EMBODIMENTS

[0018] For clarity of exposition, the drawings are not drawn to anyuniform scale. In particular, vertical and horizontal scales may bedifferent, and thus angles may be smaller or larger than in devices asfabricated, but angles described in the following description are shownin the drawings at scales suitable for clarity.

[0019] The invention is described herein first in terms of a generalstructure, associated methods of fabrication, and methods of use, andthen in terms of various specific embodiments, including memorystructures and associated methods. A person skilled in the field ofintegrated circuits will understand that corresponding structures may bemade and corresponding methods of the invention may be practiced invarious kinds of integrated circuits, such as the programmable logicarray (PLA) integrated circuits, the hybrid integrated circuits, or thestacked modules mentioned above.

[0020] One aspect of the invention is an interconnection structurehaving first and second sets of wiring channels disposed in generallyparallel planes and a third set of wiring channels oriented obliquely tothe parallel planes, the wiring channels of the third set being adaptedfor electrically coupling selected wiring channels of the first set withselected wiring channels of the second set. This aspect is exemplifiedby various particular embodiments described below.

[0021] An embodiment of a structure 10 made in accordance with theinvention may be used in integrated circuits. In this embodiment of theinvention (illustrated in FIGS. 1-5), the interconnection structure 10comprises a first array 20 of cells 30 and at least a second array 40 ofcells 50, and interconnections 60 disposed for connecting cells of thefirst array with cells of the second array. Cells 30 and 50 are normallyof the same type. First array 20 is disposed generally in a plane 70,and second array 40 is disposed generally in a plane 80, generallyparallel to plane 70. Arrays 20 and 40 may be separated by an insulatinglayer 35. At least some of those interconnections 60 are disposed alongaxes 90 oriented obliquely to the planes 70 and 80 of first and secondarrays 20 and 40. That is, the axes 90 along which the interconnections60 are arranged are at an oblique angle 100 (neither parallel norperpendicular) to the planes of the arrays. Each of the interconnections60 is selectively coupled by an electrical coupling to a cell 30 or 50of each array. The electrical coupling may simply be an ohmicconnection, for example. Each cell of the arrays may include asemiconductor device, such as a diode or transistor. The cells of thearrays may function as logic gates, memory cells, or perform some otheruseful function.

[0022]FIG. 1 shows a schematic diagram illustrating elements of a memory110 to which interconnection embodiments made in accordance with theinvention may be applied. Memory cells 120 in such structures may be ofa type having a storage element 130, such as a capacitor, and a controlelement 140, such as a diode or a switching transistor. As is known inthe art, the function of the storage element may be provided by built-incapacitance intrinsic to the physical structure, instead of by adiscrete capacitor device. The storage element 130 of each memory cell120 may be connected in series with the control element 140 of thatmemory cell. In some read-only memories (ROM's), no control element isneeded. In some embodiments, e.g., write-once memories, the controlelement 140 may be integral (at least initially) with the storageelement 130 rather than being a distinct discrete structure. Memorycells 120 are arranged in multiple arrays on parallel layers or planessuch as planes 70 and 80.

[0023] A suitable memory cell 120 may include, for example, a controlelement in series with a voltage breakdown element. The control elementmay be, for example, an electrically linear resistive element, i.e., anelement that has a linear change in current for a linear change involtage. The voltage breakdown element may be an antifuse, i.e., anelement whose resistance is normally high, and switches to alow-resistance when a suitable signal is applied. Various antifuses areknown in the art, being disclosed, for example, in U.S. Pat. Nos.5,821,558 and 6,111,302.

[0024] The control element can be composed of various materials, such asa refractory metal silicide nitride (e.g., tungsten silicide nitride),intrinsic silicon, or lightly doped microcrystalline silicon or lightlydoped amorphous silicon. The latter material, lightly doped amorphoussilicon, can reversibly enhance its current flow by lowering itsresistance when a suitable voltage is applied, allowing such an elementto function as a switch. In application of this function in a memory,all memory cells (e.g., all the control elements) in a row conductor areturned on when the row conductor is energized because all the controlelements reach a relatively low resistance. Conversely, the memory cellsthat are not selected by being energized will maintain a relatively highresistance. Memory cell 120 may include a “phase change” material thatcan be electrically switched between generally amorphous and generallymicrocrystalline states, such as the materials disclosed in U.S. Pat.Nos. 3,271,591 and 3,530,441. Application of such materials to memoriesis known in the art and disclosed in U.S. Pat. No. 4,499,557; U.S. Pat.No. 4,599,705, and U.S. Pat. No. 5,335,219, for example. The voltagebreakdown element may be composed of an electrically insulating materialsuch as oxide-nitride-oxide (ONO), tantalum pentoxide (Ta₂O₅),plasma-enhanced silicon nitride, titanium oxide, germanium oxide, or achemical-vapor-deposited (CVD) dielectric including a deposited oxide, agrown oxide, or similar dielectric materials.

[0025] Another suitable memory cell 120 may include a tunnel junctiondevice. A tunnel junction device has electrical characteristics suchthat, for linear increases in voltage, the tunnel junction exhibits anexponential increase in current. Such a memory cell has an advantage inaccess speed over many other types of cells, since it is capable ofbeing accessed in a time of the order of a few nanoseconds or less.

[0026] In memory 110, row conductors and column conductors form anorthogonal set of wiring channels, and individual memory cells areaddressed by a combination of a row conductor, e.g., a word line, and acolumn conductor, e.g., a bit line.

[0027] It will be recognized that other types of integrated circuits,such as field-programmable gate arrays (FPGA's) also require wiringchannels to address their cells, such as the individual gates of thegate array.

[0028] As shown in FIG. 1, memory 110 has a set of row conductors suchas row conductors 170, 180, 190, 200, and 210 and a set of columnconductors such as column conductors 220, 230, 240, 250, and 260,arranged parallel to layers or planes such as planes 70 and 80. Each rowconductor can be a word line for memory 110, and each column conductor abit line.

[0029] While only a few memory cells, planes, row conductors, and columnconductors are shown in FIG. 1, it will be understood that memory 110may consist of many such elements, and the arrangement depictedschematically in FIG. 1 may be extended both in the two directions(e.g., along conventional x- and y-axes parallel to each plane) andalong a z-axis perpendicularly to the planes, i.e., having multipleplanes.

[0030] In addition to the row and column conductors, a set of verticalinterconnections or pillars 300 may be provided (FIG. 3), extending fromone plane to another for connecting one or more memory cells in a firstplane with one or more memory cells in another plane. In conventionalmemories, such vertical interconnections or pillars 300 are arrangedalong axes 310 oriented generally perpendicularly to the planes.

[0031] In an interconnection structure embodiment made in accordancewith the invention, each cell of an array is disposed at theintersection of an obliquely angled pillar conductor 400 or astair-stepped pillar conductor 410 with one of the arrays of cells.Interconnection 60 comprises a series of conductors or conductivepillars 400 and/or 410. When obliquely angled conductors 400 areemployed, as shown in FIG. 2, the axis 420 of each pillar itself isoblique to the planes of the arrays, and the associated pillars aresubstantially aligned along a common oblique axis 90.

[0032] In an interconnection 60 comprising a series of stair-steppedpillar conductors 410, as shown in FIG. 3, the position of eachassociated pillar 410 is along an axis 90 oblique to the planes of thearrays, but the axis 440 of each pillar itself is not aligned parallelto the oblique axis 90. In particular, the axis 440 of each pillar ofthe stair-stepped conductors may be substantially perpendicular to theplane of the arrays, as it is in the example shown in FIG. 3. In theembodiment of FIG. 3, interconnections 60 may also include conductivetrace segments 430 on, within, or parallel to the plane 70 or 80 of eacharray 20 or 40 for connecting associated pillars.

[0033] It will be recognized that the embodiments shown in FIGS. 2 and 3are not mutually exclusive, but represent two types of interconnectionwhich may be combined in a single interconnection structure. Thus, astructure 60 made in accordance with the invention may include not onlyobliquely angled pillar conductors 400 substantially parallel to obliqueaxis 90, and stair-stepped pillar conductors 410 substantiallyperpendicular to planes 70 and 80, but also pillar conductors whoseindividual pillar axes 440 have neither of those orientations. Thelatter individual pillar axes 440 may be made oblique to both axis 90and planes 70 and 80 (e.g., at an intermediate angle).

[0034] FIGS. 4A-4C show various schematic views of a first embodimentincluding interconnections made in accordance with the invention. FIG.4A is a schematic perspective view showing arrays of memory cells 120arranged in a three-dimensional configuration and interconnected bystair-stepped pillar interconnections 410. The interconnections 410shown in FIG. 4A are disposed along axes obliquely oriented with respectto the planes of the arrays in which memory cells 120 are arranged. Aschematic end elevation view of the embodiment of FIG. 4A is shown inFIG. 4B, and a schematic side elevation view of the same embodiment isshown in FIG. 4C. As shown in FIGS. 4A and 4C, all of theinterconnections 410 are disposed along oblique axes that are parallel.FIGS. 4A-4C show vertically stacked rows 450 along with row select linesSEL 0 (460), SEL 1 (461), SEL 2 (462), and SEL 3 (463), basesemiconductor control devices 456, and sense amplifiers 455 selectivelyconnected to V_(array) (457) with associated outputs OUT 0 (480), OUT 1(481), and OUT 2 (482). Also shown in FIGS. 4A-4C are rows 0M (470), 1M(471), 2M (472), 3M (473), 4M (474), 5M (475), 6M (476), 7M (477), and8M (478); and row 0-8 planes (500-508), each of which includes layersL1, L2, and L3 (identified by reference numerals 491, 493, and 494 onlyfor row 0 (500) and reference numeral 492 only for row 4m (470)).

[0035] As shown in schematic end view, FIG. 4B, memory cells 120 arearranged generally aligned in the vertical direction and in parallelplanes. As shown in schematic side view, FIG. 4C, stair-stepped verticalpillar interconnections 410, interconnecting memory cells 120 of thearrays are disposed along axes oblique to the planes of memory cells120. FIGS. 4A and 4C show select line 460, sense amplifiers 455, basesemiconductor control devices 456, and, along the bottom of FIG. 4C, aset of row selection lines corresponding to the rows of the array, e.g.,470, 471, 500, and 501.

[0036] FIGS. 5A-5C show various schematic views of a second embodimentincluding interconnections made in accordance with the invention. Thisembodiment differs from the embodiment shown in FIGS. 4A-4C in havingtwo alternating orientations of axes oblique to the planes of memorycells 120 instead of having all the stair-stepped vertical pillarinterconnections 410 disposed parallel to each other as they are inFIGS. 4A-4C. As shown in FIGS. 5A and 5C, stair-stepped vertical pillarinterconnections 410 are disposed along a first axis oblique to theplanes of memory cells 120, while stair-stepped vertical pillarinterconnections 415 are disposed along a second axis oblique to theplanes of memory cells, where the second axis is inclined in theopposite direction from the vertical. That is, the oblique axes of thetwo sets of stair-stepped vertical pillar interconnections in FIGS. 5Aand 5C are opposed.

[0037]FIG. 5C illustrates an advantageous feature of this arrangement:the base semiconductor element 456 may be combined for two pillars andshared by the two pillars. For example, the two base semiconductorelements 456 indicated in FIG. 5C by large arrows and dashed circles maybe shared. Base semiconductor control devices 456 are selectivelyconnected to V_(array) (457) through sense amplifiers 455. Otherwise,except for this feature of shared base semiconductor elements and theopposed oblique axes of its vertical pillar interconnections, theembodiment of FIGS. 5A-5C is similar to the embodiment of FIGS. 4A-4C.In particular, the end view of the embodiment of FIGS. 5A-5C isessentially the same as FIG. 4B.

[0038] Both of these embodiments have improved volumetric memory cell tointerconnection efficiency, i.e., the ratio of memory cell volume tointerconnection volume, over prior-art interconnections: e.g., 75% ascompared to 50% for a prior-art interconnection structure. With respectto utilization of base silicon area, the embodiment of FIGS. 4A-4Crequires only one-third as many base semiconductor devices 456 as aprior-art interconnection structure. By virtue of the device sharingdescribed above, the embodiment of FIGS. 5A-5C requires only one-sixthas many base semiconductor devices as a prior-art interconnectionstructure.

[0039] While a few memory cells, planes, row conductors, and verticalpillar interconnections are shown in FIGS. 4A-4C and 5A-5C, it will beunderstood that memory 110 may consist of many such elements, and thatthe arrangements depicted schematically in FIGS. 4A-4C and 5A-5C may beextended both in the two in-plane directions (e.g., along conventionalx- and y-axes parallel to each plane) and along a z-axis perpendicularlyto the planes. One of the advantages provided by the obliquely angledpillar interconnections and stair-stepped pillar interconnections of thepresent invention is that extensibility along the Z-axis is essentiallyunlimited, by virtue of the constant vertical-interconnection overhead.

[0040] Thus, an integrated circuit may be made having at least twoarrays of cells, with the cells of the arrays being selectivelyinterconnected by an interconnection structure as described herein. Thisinterconnection structure is not merely a set of staggered pillars. Eachpillar in an interconnected set is disposed along the same oblique axisextending from the lowest connected layer to the highest connectedlayer. Specifically, a memory may be made with the memory cells or nodesselectively interconnected by such an interconnection structure, and amass storage device may be made from such memories. A description offabrication methods follows.

Fabrication Methods

[0041] Another aspect of the invention is a method for fabricating aninterconnection structure. An embodiment of such a method is illustratedby the flow chart of FIG. 6.

[0042] Embodiments of the integrated circuits using the interconnectionstructure of the invention are fabricated upon a conventional supportingstructure such as a flat silicon semiconductor wafer substrate (notshown). Alternatively, the substrate may be made of glass, polymer,plastic, gallium arsenide, silicon on sapphire (SOS), epitaxialformations, germanium, germanium silicon, diamond, silicon on insulator(SOI) material, selective implantation of oxygen (SIMOX) substrates,and/or like substrate materials. Base semiconductor devices may becrystalline or non-crystalline.

[0043] The overall method shown in FIG. 6 comprises steps of forming afirst array of cells (S1), forming at least a second array of cellsparallel to the first array (S2), and selectively connecting individualcells of the first array with individual cells of the second array byconductive interconnections disposed obliquely to the arrays (S3). Inthis method, forming steps S1 and S2 are performed by disposing thefirst array of cells in a first plane (substep S4) and disposing thesecond array of cells in a second plane (substep S5) parallel to thefirst plane. Steps S1, S2, S4, and S5 may be performed by conventionalsemiconductor integrated circuit fabrication processes, includingpatterning (by photolithography, for example), and deposition of knownsubstances. Conductive elements such as row conductors may be formed bydepositing and patterning a conductive material: aluminum, copper,copper-aluminum alloy, silicide, amorphous silicon, microcrystallinesilicon, or a refractory metal such as tungsten or an alloy thereof.Such row conductors may have a thickness in a typical range from about20 nanometers (200 Angstroms) to about 500 nanometers (5000 Angstroms),typically about 180 nanometers (1800 Angstroms).

[0044] Electrically insulating layer 35 may be composed, for example, ofa material such as wet or dry silicon dioxide (SiO₂), a nitride materialsuch as silicon nitride, tetraethylorthosilicate (TEOS) based oxides,borophosphosilicate glass (BPSG), phosphosilicate glass (PSG),borosilicate glass (BSG), polyimide film, polyamide film, oxynitride,spun-on glass (SOG), a chemical vapor deposited (CVD) dielectricincluding a deposited oxide, a grown oxide, or similar dielectricmaterials. When composed of TEOS based oxides, insulating layer 35 canbe formed by a deposition resulting from the decomposition of a TEOS gasin a reactor.

[0045] Connecting step S3 is performed by disposing the conductiveinterconnections along first and second axes (substeps S6 and S7respectively), at least one of these axes being oriented obliquely tothe first and second planes. One or both of the first and second axesmay be oriented obliquely to the first and second planes in substeps S6and S7. Each of the axes oriented obliquely to the first and secondarrays forms an angle between about 30 degrees and about 60 degrees,e.g., about 45 degrees, with at least one of the first and secondarrays. If the arrays are in the common parallel relationship, the axesform the same angle with each array.

[0046]FIG. 7 shows a side elevation cross-sectional view of a portion ofan embodiment, illustrating a particular method for performing step S6and S7. An oblique opening 800 is formed in insulating layer 35, bydirectionally etching through openings in a patterned mask 815 and alonga direction 810 parallel to desired oblique axis 90. This may be areactive ion etch, for example. Opening 800 extends down to a conductiveportion of cell 50. Opening 800 is filled with a conductive substance toform conductive pillar 400, and if necessary, the conductive substanceis planarized to be flush with the top surface of insulating layer 35 toprepare for subsequent fabrication operations.

[0047]FIG. 8 shows a cutaway perspective view of a portion of anotherembodiment, illustrating another method for performing fabrication stepsS6 or S7. As shown in FIG. 8, a V-shaped groove with sidewalls 820oriented at a desired angle suitable for oblique axes 90 is patternedand etched into insulating layer 35. Deposition and patterning of aconductive substance then forms conductive portions 830 suitablyoriented to form segments of conductive pillars 400 and, if necessary,may also form horizontal trace segments 430 on the surface of insulatinglayer 35. The V-shaped groove may be filled with an insulating substancein a subsequent processing step if necessary and then planarized ifnecessary. To facilitate electrical connection with a conductive traceon the lower layer (below insulating layer 35), the opening may be madewith a trapezoidal cross-section instead of the V-shaped groove shown.

[0048] In the following paragraphs of this description, two methods ofperforming substeps S6 and S7 are distinguished. A decision (S8) is madeas to which method to perform. In the first method, illustrated in FIG.4, the first and second axes are made substantially parallel (S9). Sucha method provides some advantages, such as being capable ofimplementation with simpler masks, having improved volumetricefficiency, and using fewer base devices 456 than a prior-artinterconnection structure, as explained further herein.

[0049] In the second method of performing substeps S6 and S7, the firstand second axes are made non-parallel to each other (S10). In aparticular variation of this second (non-parallel) method of performingsubsteps S6 and S7, the first and second axes are made opposed (S12).That is, if this method is selected (S11), the first and second axes aremade to slant obliquely in opposite directions from a (third) referencedirection perpendicular to the planes of the array, whereby the firstand second axes may be said to slant away from (opposed to) each other.A structure made by the latter method is illustrated in FIG. 5. Theembodiment illustrated in FIG. 8 also has opposed axes. This secondmethod of making the interconnection structure provides some additionaladvantages (besides having improved volumetric efficiency), such asallowing a design using even fewer base devices 456 than are needed inthe first method using parallel axes. The base-device sharing that makesthis improvement possible is described hereinabove.

[0050] Another distinct advantage provided by the method of orientingthe axes at opposed oblique angles is reduced capacitive couplingbetween the opposed interconnections and, thus, higher speed and lesstendency for crosstalk. In comparison with prior-art interconnectionstructures, parasitic capacitance is greatly reduced, at least partiallydue to minimization of the effective total area of overlap betweenadjacent vertical interconnections. In particular, as shown in theembodiment of FIG. 5A, a multiplicity of pairs of first and second axesmay be disposed in alternating opposed relationship, whereby no firstaxis is adjacent to a parallel second axis. Thus, in FIG. 5A, everyother axis of conductive connections slants in the opposite direction.This has the beneficial result of minimizing overlapping area betweentheir respective conductive connections, which thus minimizescapacitance between their respective conductive connections, and thusalso increases speed and minimizes crosstalk that otherwise could occurbetween their respective conductive connections.

[0051] Another aspect of performing steps S6 and S7 is the choice ofwhether each conductive connection between the arrays is made parallelto the axes discussed above (oblique pillars) or is made non-parallel tothe axes (stair-stepped pillars). Thus, in step S6, each conductiveinterconnection along the first axis may be made in the form of a pillarparallel to the first axis, and therefore oblique relative to the planesof the arrays. Similarly, in step S7, each conductive interconnectionalong the second axis may be made in the form of a pillar parallel tothe second axis and thus oblique to the planes of the arrays. On theother hand, step S6 may be performed by making each conductiveinterconnection along the first axis in the form of a pillarsubstantially perpendicular to the first and second array planes andparallel to the reference, whereby the conductive interconnections forma stair-stepped set of interconnections. Again, similarly, step S7 maybe performed by making each conductive interconnection along the secondaxis in the form of a pillar substantially perpendicular to the firstand second planes and thus parallel to the reference direction mentionedabove, whereby those conductive interconnections form a stair-steppedset of interconnections. A person skilled in integrated circuitfabrication will recognize that various combinations of parallel andnon-parallel axes and/or oblique and stair-stepped pillar structures maybe employed to adapt the methods of the invention to various purposes.

MEMORY EMBODIMENT EXAMPLE

[0052] One aspect of a memory embodiment of the present invention is anarchitecture to support interconnections between multiple layers in avertical axis above base silicon circuits. Such a memory embodiment,illustrated by FIGS. 4A-4C or FIGS. 5A-5C, may be termed a “verticalmemory” or “vertically oriented memory.” The memory has word lines, bitlines, and base control devices 456 (e.g., FET devices) for multiplexingthe bit lines.

[0053] In this memory embodiment, multiple angled or stair-steppedvertical pillars access the various layers, and the memory is comprisedof storage elements or nodes formed at the intersections of the multipleangled or stair-stepped vertical pillar access interconnection structurewith the word lines within the memory layers. Thus, multiple angled orstair-stepped vertical pillars are utilized to access cells of avertically oriented memory array. Each cell may be a conventional “1T”DRAM memory cell having a single MOS switching transistor and a storagecapacitor, for example.

[0054] A particular embodiment for write-once memory arrays includesstructures in which a vertical pillar performs the function of thecolumn or bit line and addresses a tunnel junction device. A rowconductor is formed either above or below the obliquely angled orstair-stepped vertical pillar conductor. A control element is formedbetween a row conductor and the obliquely angled or stair-stepped pillarconductor. A single memory storage element or plurality of memorystorage elements is formed at an intersection of the obliquely angled orstair-stepped pillar conductor with a row conductor.

[0055] Various other embodiments may be made, employing interconnectionstructures formed according to the present invention. For example,multiple-layer obliquely angled or stair-stepped pillars can access avertical memory array having a plurality of rows stacked in the Zdimension (i.e., perpendicular to the substrate), with memory elementsformed at the intersections of the angled or stair-stepped pillarconductor with each of the stacked rows. Each memory cell, consisting ofa series-connected storage element and control element, is constructedat the intersection of the obliquely angled or stair-stepped pillarconductor and one of the stacked rows. The memory element may comprise aresistive storage element in series with a resistive control element.

[0056] In such an array, a semiconductor control element at the base ofeach angled or stair-stepped pillar interconnection is selectable to bitlines via row control lines. More than one pillar interconnection may beshared with a base semiconductor device, as, for example, when obliquelyangled pillar interconnections are constructed at opposing angles tomaintain access to individual memory elements. Thus, fewer basesemiconductor control devices are needed in such an array. Typicallyonly one-third of the number of base semiconductor control devices areneeded, compared with structures using conventional pillarinterconnections.

[0057] In a related embodiment, the storage element can comprise atunnel-junction oxide that exhibits a high off-state resistance beforebeing fused and exhibits a low on-state resistance after being fusedwith sufficient energy to form a low resistance filament between theelectrodes. Similarly, the control element can comprise atunnel-junction oxide that exhibits a high read-state resistance and alow write-state resistance.

[0058] Supporting circuitry may be provided for memory made inaccordance with the invention, including provision for row controlselection of pillars, common drive interconnection, and/or sense lines.Each pillar conductor may have a semiconductor control device connectedat its base. In one embodiment, the semiconductor device connected atthe base of each pillar is a field-effect transistor (FET) whose gate iscontrolled by a device external to the array. Row control elementscontrol the gates of the pillar FET's across a row through the array.Each pillar is selectable by means of a line or lines orthogonal to therow control lines.

[0059] The supporting circuitry for obliquely angled or stair-steppedpillar access memory can provide multiplexing of horizontally orvertically oriented column interconnection lines in the layers of memorythat intersect with the obliquely angled or stair-stepped pillarconductors. The layers of horizontal or vertically orientedinterconnections through the vertical memory layers are controlled byconventional functional elements external to the array and operated indrive mode or sense mode. When these interconnection lines are used insense mode, the functional elements external to the array comprise senseamplifier circuits for read and write current comparisons. These linescan also be used to provide read and write voltage references, in whichcase the functional elements external to the array comprise the read andwrite voltage reference sources and multiplexing.

[0060] While the structure has been described beginning with a simpleembodiment having two layers, other embodiments may have a multiplicityof arrays, each array being disposed in a layer. Thus, cells on amultiplicity of layers are selectively interconnected, as illustrated inthe embodiments of FIGS. 2 and 3. For some applications, the structuremay have two to eight layers, for example. Other embodiments of thestructure may have from eight to twelve layers. Unlike many otherstructures known in the art, which have an overhead cost associated witheach layer, there is no known limit to the number of layers that can beaccommodated in a structure made in accordance with the presentinvention. Thus, there may be even more than twelve layers, the numberof layers being essentially unlimited.

Industrial Applicability

[0061] The interconnection structures of the invention are especiallyuseful in semiconductor devices such as memory integrated circuits.Integrated circuits of many types, including such integrated circuittypes as the memory embodiment example described above, may be made withinterconnection structures fabricated in accordance with the invention.Such structures and integrated circuits employing them are useful inapparatus such as mobile or stationary telephones, digital cameras andcamcorders, computing devices (such as desktop and portable computers,calculators, and personal digital assistants (PDA's) and theirperipheral devices), media players such as players for CD's, DVD's,music, and video, and apparatus for printing, scanning, storing,copying, facsimile reproduction, and transmitting of documents. Thelatter apparatus may include multifunction devices.

[0062] Other embodiments of the invention will be apparent to thoseskilled in the art from a consideration of this specification or frompractice of the invention disclosed herein. For example, obliquelyangled or stair-stepped pillars may be arranged along multiple sets ofpairwise-parallel oblique axes and/or multiple sets of pairwise opposedoblique axes. It is intended that the specification and examplesdisclosed herein be considered as exemplary only, with the true scopeand spirit of the invention being defined by the following claims.Accordingly, the scope of the invention should be determined not by theembodiments illustrated, but by the appended claims and their legalequivalents.

What is claimed is:
 1. An interconnection structure comprising: a) afirst set of wiring channels disposed in a first plane, b) a second setof wiring channels disposed in a second plane generally parallel to saidfirst plane, and c) at least a third set of wiring channels orientedobliquely to said first and second planes, the wiring channels of saidthird set being adapted for electrically coupling selected wiringchannels of said first set with selected wiring channels of said secondset.
 2. A structure for integrated circuits, said structure comprising:a) a first array of cells, b) at least one second array of cells, and c)interconnections adapted for electrically coupling cells of said firstarray with cells of said second array, at least some of saidinterconnections being disposed along axes oriented obliquely to saidfirst and second arrays and being electrically coupled to each other. 3.A structure as in claim 2, wherein each of said interconnections isselectively coupled by an electrical coupling to a cell of said firstarray.
 4. A structure as in claim 2, wherein each of saidinterconnections is selectively coupled by an electrical coupling to acell of said second array.
 5. A structure as in claim 2, wherein each ofsaid axes oriented obliquely to said first and second arrays forms anangle with one of said first and second arrays, said angle being betweenabout 30 degrees and about 60 degrees.
 6. A structure as in claim 5,wherein each of said axes oriented obliquely to said first and secondarrays forms an angle of about 45 degrees with one of said first andsecond arrays.
 7. A structure as in claim 2, comprising a multiplicityof arrays, each array of said multiplicity being disposed in a layer,whereby cells on a multiplicity of layers are selectivelyinterconnected.
 8. A structure as in claim 7, wherein said multiplicityof layers comprise from two to eight layers.
 9. A structure as in claim7, wherein said multiplicity of layers comprise from eight to twelvelayers.
 10. A structure as in claim 7, wherein said multiplicity oflayers comprise twelve or more layers.
 11. A structure as in claim 2,wherein said at least some of said interconnections are adapted toprovide a volumetric efficiency of 75%.
 12. A structure as in claim 2,wherein each cell of said cells of said first and second arrayscomprises a semiconductor device.
 13. A structure as in claim 2, whereinsaid cells of said first and second arrays are memory cells.
 14. Astructure as in claim 13, wherein each cell of said cells of said firstand second arrays comprises a semiconductor device.
 15. A structure asin claim 13, wherein each of said memory cells comprises a storageelement and a control element.
 16. A structure as in claim 15, whereinsaid storage element of each memory cell is connected in series withsaid control element of that memory cell.
 17. A structure as in claim13, wherein each memory cell is disposed at the intersection of anangled vertical pillar conductor with one of said first or second arraysof cells.
 18. A structure as in claim 13, wherein each memory cell isdisposed at the intersection of a stair-stepped vertical pillarconductor with one of said first or second arrays of cells.
 19. Anintegrated circuit comprising at least two arrays of cells, said cellsof said arrays being selectively interconnected by a structure asrecited in claim
 2. 20. A memory comprising at least two arrays ofcells, said cells of said arrays being selectively interconnected by astructure as recited in claim
 2. 21. A mass storage device comprising atleast one memory as recited in claim
 20. 22. A structure for integratedcircuits, said structure comprising: a) a multiplicity of arrays ofcells, each array of said multiplicity being disposed in a layer, saidmultiplicity of arrays including a first array of cells disposed in afirst layer and at least one second array of cells disposed in a secondlayer, and b) interconnections adapted for electrically coupling cellsin said first layer with cells of at least said second layer, at leastsome of said interconnections being disposed along axes orientedobliquely to said first and second layers and being electrically coupledto each other, whereby cells in a multiplicity of layers are selectivelyinterconnected.
 23. A structure for integrated circuits, said structurecomprising: a) a first array of cells, b) at least one second array ofcells, and c) interconnections adapted for electrically coupling cellsof said first array with cells of said second array, at least some ofsaid interconnections being disposed along axes oriented obliquely tosaid first and second arrays and being electrically coupled to eachother, said at least some of said interconnections being further adaptedto share a number of base semiconductor devices, said number beingone-third to one-sixth of a quantity of base semiconductor devices usedotherwise without sharing.
 24. A method for fabricating a structure,said method comprising the steps of: a) forming a first array of cells,b) forming at least a second array of cells generally parallel to saidfirst array, and c) selectively coupling individual cells of said firstarray with individual cells of said second array by conductiveinterconnections disposed along at least one axis oriented obliquely tosaid first and second arrays.
 25. A structure fabricated by the methodof claim
 24. 26. The method of claim 24, wherein said forming steps (a)and (b) are performed by disposing said first array of cells in a firstplane and disposing said second array of cells in a second planeparallel to the first plane.
 27. The method of claim 26, wherein saidselective coupling step (c) is performed by disposing said conductiveinterconnections along first and second axes, at least one of said axesbeing oriented obliquely to said first and second planes.
 28. The methodof claim 27, wherein both of said first and second axes are orientedobliquely to said first and second planes.
 29. The method of claim 27,wherein said first and second axes are parallel.
 30. A structurefabricated by the method of claim
 29. 31. The method of claim 27,wherein said first and second axes are non-parallel.
 32. The method ofclaim 31, wherein said first and second axes slant in oppositedirections from a third axis perpendicular to said first and secondplanes, whereby said first and second axes are opposed.
 33. The methodof claim 32, wherein a multiplicity of pairs of said first and secondaxes are disposed in alternating opposed relationship, whereby no firstaxis is adjacent to a parallel second axis.
 34. The method of claim 32wherein said first and second axes are suitably disposed to minimizeoverlapping area between their respective conductive connections. 35.The method of claim 32 wherein said first and second axes are suitablydisposed to minimize capacitance between their respective conductiveconnections.
 36. The method of claim 32 wherein said first and secondaxes are suitably disposed to minimize crosstalk between theirrespective conductive connections.
 37. A structure fabricated by themethod of claim
 31. 38. The method of claim 27, wherein each conductiveinterconnection along said first axis is made in the form of a pillarparallel to said first axis.
 39. The method of claim 27, wherein eachconductive interconnection along said second axis is made in the form ofa pillar parallel to said second axis.
 40. The method of claim 27,wherein each conductive interconnection along said first axis is made inthe form of a pillar substantially perpendicular to said first andsecond planes, whereby said conductive interconnections form astair-stepped set of interconnections.
 41. The method of claim 27,wherein each conductive interconnection along said second axis is madein the form of a pillar substantially perpendicular to said first andsecond planes, whereby said conductive interconnections form astair-stepped set of interconnections.
 42. A structure for integratedcircuits, said structure comprising: a) a first array of cells, b) atleast one second array of cells, and c) interconnections disposed forconnecting cells of said first array with cells of said at least onesecond array, at least some of said interconnections being disposedalong axes oriented obliquely to said first and second arrays, each ofsaid interconnections being selectively connected by an electricalconnection to a cell of at least one of said first and second arrays,said electrical connection comprising an element selected from the listconsisting of an ohmic connection, a switching device, a semiconductordevice, a diode, a field-effect transistor, an antifuse, and a fusibleelement.
 43. An integrated circuit comprising at least two arrays ofcells, said cells of said arrays being selectively interconnected byinterconnections adapted for electrically coupling cells of said firstarray with cells of said second array, at least some of saidinterconnections being disposed along axes oriented obliquely to saidfirst and second arrays and being electrically coupled to each other.44. A memory comprising at least two arrays of cells, said cells of saidarrays being selectively interconnected by interconnections adapted forelectrically coupling cells of said first array with cells of saidsecond array, at least some of said interconnections being disposedalong axes oriented obliquely to said first and second arrays and beingelectrically coupled to each other.
 45. A mass storage device comprisingat least one memory, said memory comprising at least two arrays ofcells, said cells of said arrays being selectively interconnected byinterconnections adapted for electrically coupling cells of said firstarray with cells of said second array, at least some of saidinterconnections being disposed along axes oriented obliquely to saidfirst and second arrays and being electrically coupled to each other.46. An interconnection structure comprising: a) a first set of wiringmeans disposed in a first plane, b) a second set of wiring meansdisposed in a second plane generally parallel to said first plane, andc) means for electrically coupling selected wiring means of said firstset with selected wiring means of said second set, said means forelectrically coupling being disposed along at least one axis orientedobliquely to said first and second planes.